VHDL and ASIC Design
Prepared By: James Swift, Staff Eng, IBM Microelectronics Division
Send your comments to jswift@vnet.ibm.com
Copyright 1995, James Swift Copying this document without the permission of the author is prohibited and a violation of international copyright laws.
Description
Students will become familiar with the VHDL language through text readings and lectures following the basic flow of the text. Students will become familiar with the ASIC design process through supplemental readings, lectures and execution of a design project from conceptualization to technology netlist ready for fabrication and described in VHDL.
To Reach Me
email Internet : jswift@vnet.ibm.com
Inside IBM : http://w3.btv.ibm.com/~jswift/e-mail.html <-- press here to send mail phone: 802-769-6490 (W) 434-2880 (H) Text: 'VHDL - 2nd Edition', D Perry, Mcgraw-Hill Prerequisites
UVM EE131 Fundamentals of Digital Design or equiv Logic Design Course
UVM CS21 or CS26 Computer Programming or equiv C Programming Course
Course Outline
Introduction - What is VHDL? What is an ASIC? Read Chap 1
Project Definition - Establish teams, Define project, Features, Discuss Function vs Cost. Skim Chaps 11 & 12
Behavioural Modeling With Concurrent Statements & Expressions - Read Chap 2 + assignment and Appendix C
ASIC Methodology
Design Tools
Review Basic Design Steps
Sequential Processing - Read Chap 3 + assignment
Data Types - Read Chap 4 + assignment
Project Lab - Coding & Analyzing
Subprograms - Read Chap 5 + assignment
Attributes - Read Chap 6
Project Lab - Simulation
Simulation Survey - Interpretive vs Compiled Native Code Behavioural, Gate Level, Boolean Equivilance VITAL,
Configuration - Read Chap 7
Advanced Topics - Read Chap 8
Project Lab - Synthesis
Synthesis Survey - Technology Mapping, Logic Optimization, Delay Calculation, Area/Performance Trade Off, New IEEE Package, Common Problems Clock Networks
IEEE 1076-1993 Updates to the VHDL Language Standard -
Testability Survey - Examination of Test techniques and CMOS implimentations. LSSD, Latches vs Flip-Flops, JTAG, ABIST, LBIST VHDL Coding Techniques, Specialized Design Tools, Common Problems.
Project Lab - Synthesis continued
Project Lab - Final Netlist Creation
Roster
Fall 95
Acknowledgements
Source: www.emba.uvm.edu/~jswift/
