Synthesis with Hardware Design Languages
Copyright 1998, Ben M. Huey Copying this document without the permission of the author is prohibited and a violation of international copyright laws.
Course Syllabus
Lectures
Introduction and Overview, 1/20
Primitive elements, design modules, 1/22
Concurrent signal assignment, 1/27
Concurrent constructs and structural equivalents #1, 1/29
Data structures , 2/3
Operators, attributes, constants , 2/5
Concurrent constructs: Functions, procedures, guards and bus resolution, 2/10
Concurrent constructs: Iteration and recursion, 2/12
Introduction to Processes, 2/17 (Lab #1)
Sequential flow of control, 2/19
Introduction to Synthesis Tools, 2/24
Tutorial Introduction to Synthesis with Autologic II
Structural VHDL , 2/26
Configuration in VHDL , 3/3
Synchronous Controllers: Finite state machines, 3/5-10
Tutorial Introduction to Synthesis with Autologic II, Chap. 5
Term Projects / Teams Assigned, 3/10
Progress report due 4/7, Final report due 4/25
Examination #1, 3/12
Examinations from previous years posted here can be used as study guides. The course this year is covering some of the CSE 517 material from earlier years, and slightly less of the synthesis material than in 1996, but the nature of the questions will be similar.
Exam #1, CSE 518, Spring 1995 (solution)Exam #1, CSE 517, Spring 1996 (solution)
SPRING BREAK 3/15-21
Exam review, formation of groups for term projects, 3/24
Lab #3 assigned, Due 3/31
Area and performance strategies for optimization, 3/26
Lab #2 assigned, Due 4/7
Timing Optimization #1, 3/31
Timing Optimization #2, 4/2
Design Partitioning #1, 4/7
Design Partitioning #2, 4/9
To be determined, 4/14-23
Term Project Presentations, 4/25-5/3
Final Exam , 12:20-2:10 p.m., Thursday, May 14
Laboratories
Laboratory #1
In this laboratory you will become familiar with the software, and get an idea of how one uses a synthesis tool and kinds of output it provides.
Laboratory #2
Synthesis of combinational logic: Control of optimization
Final ProjectThe choices for final projects are as follows:
Option #1: Microcontroller
Option #2: Arithmetic / Logic Unit
Option #4: Banyan Switch for ATM
Option #5: Intel 82370 Text CoProcessor
Option #6: AMD 293xx Multiplier
Reference materials
Std_logic Packages
IEEE Standard 1164: Package Header
IEEE Standard 1164: Package Body
Mentor Std_logic Extensions: Package Header
Mentor Std_logic Extensions: Package Body
Mentor Std_logic Arithmetic: Package Header
Mentor Std_logic Arithmetic: Package Body
Interesting Links
VHDL International Users' Forum
VHDL Synthesis Working Group
VLSI Related Research Institutions
Resume
Dr. Ben HueyAssociate Dean for Planning and AdministrationArizona State University Dr. Ben Huey is Associate Dean for Planning and Administration at Arizona State University, working with college level program initiatives including development of information science and technology, budget and facilities issues, and continuous quality improvement. In 2001-2002 Dr. Huey was chair of the Computing Accreditation Commission of ABET, and currently serves as a member of the CAC/ABET and with INTAC. He is a member of the Board of Directors for the Consortium for Embedded Systems, and is participating in CES and NSF sponsored curriculum development in embedded systems. He teaches courses in VLSI design which are frequently offered via instructional television, and are constantly being revised in the course of experimenting with interactive distance learning. His research is in high-level design languages for automated digital hardware synthesis, design validation, and automated test program generation. Dr. Huey received his B.S. in Mathematics from Harding University, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Arizona.
Source: Best Assessment Processes Symposium II (Rose-Human Institute of Technology, Indiana, USA)
