By Bob Reese
Electrical Engineering Department
Mississippi State University
Lectures
- Logic Synthesis
- Tutorial Caveats
- VHDL Synthesis Subset
- General Comments about VHDL Syntax
- Combinational Logic Examples
- Model Template
- 2 to 1 Mux - Using when else..
- Standard Logic 1164
- 2 to 1 Mux Entity Declaration
- 2 to 1 Mux Architecture Declaration
- 2 to 1 Mux Architecture using Booleans
- 2 to 1 Mux Architecture using a Process
- 8 Level Priority Encoder
- 3 to 8 Decoder Example
- A Common Error
- Alternative 3 to 8 Decoder
- Generic Decoder
- Synthesis Boundary Conditions
- Ripple Carry Adder
- Ripple Carry Adder Comments
- Summary