Logic Synthesis with VHDL Combinational Logic

Logic Synthesis with VHDL Combinational Logic

By Bob Reese

Electrical Engineering Department

Mississippi State University

Lectures

1. Logic Synthesis
2. Tutorial Caveats
3. VHDL Synthesis Subset
4. General Comments about VHDL Syntax
5. Combinational Logic Examples
6. Model Template
7. 2 to 1 Mux - Using when else..
8. Standard Logic 1164
9. 2 to 1 Mux Entity Declaration
10. 2 to 1 Mux Architecture Declaration
11. 2 to 1 Mux Architecture using Booleans
12. 2 to 1 Mux Architecture using a Process
13. 8 Level Priority Encoder
14. 3 to 8 Decoder Example
15. A Common Error
16. Alternative 3 to 8 Decoder
17. Generic Decoder
18. Synthesis Boundary Conditions
19. Ripple Carry Adder
20. Ripple Carry Adder Comments
21. Summary