Source-1: http://www.pldworld.com/_hdl/1/index.html
Source-2: ftp://erm1.u-strasbg.fr/vhdl
Archive List / readme
ISCAS VHDL Model (ISCAS85/89) / readme
Misc
ACRONYM LIST
VHDL Analog Extension (IEEE 1076.1)
VHDL Modeling for Analog-Digital Hardware Designs
Comparison Random Number Generator (ada) / PDF
Models .VHDL
2901.vhdl (files) / 2910.vhdl (files) / 8251.vhdl (files) / DP32.vhdl (readme) / gl85erm.vhdl (readme) / kalman.vhdl (files) / lfsr.vhdl (pdf) / multiplier.2.vhdl (pdf) / Serial-adder.vhdl (pdf) / SN54S151.vhdl (pdf) / uart-mem-and-error-by-cohen (readme) / arms-counter.vhdl / barrel.vhdl / coelho.bib.vhdl / diffeq.vhdl / dlx.vhdl / dram_8_512.vhdl / eeserv.ee.umanitoba.ca / ellipf.vhdl / float_adder / gcd_vhdl / gl85.vhdl / I80386.vhdl / IEEE_1149 / Mark2.vhdl / MASI.vhdl / mouse1.vhdl / mouse2.vhdl / multiplier.1.vhdl / Parity-set.vhdl / reg4.vhdl / tlc.vhdl / traffic-light.vhdl / uceng.uc.edu / Z80.vhdl / zycad.vhdl / Packages.vhdl / Al_Gilman_pack / Analog_lib / EIA_Types / IEEE_1164.vhdl / maths.vhdl / petri.vhdl (readme) / queue.vhdl (readme) / random1.vhdl / random2.vhdl / spice_with_vhdl / Vantage_pack / VHDL_stand.comp.lib / vhdl_synth.package (history) / WAVES
Papers
Guidelines for writing VHDL Models in a teamwork environment
Armstrong book / EPIC2 / ESA Report
Femto-VHDL.JVTassel (readme)
John Van Tassel's PhD "Femto-VHDL: The Semantics of a Subset of VHDL and its Embedding in the HOL Theorem-Prover"
IEEE Excerpt / recursive.Ashenden / Tufts university (readme)
VHDL Cookbook (readme) - PDF Document
The VHDL Cookbook First Edition (July 1990) (c) 1990, Peter J. Ashenden
Results at ERM-MACAO
Synthesis VHDL Model
These examples of syntisable designs are available on VHDL.ORG proposed by NAVABI (navabi@ece.neu.edu)(RTL models are available only here)
ORIGINAL ---- Behevioral definitions
RTL ---- RTL synthesis (Y.HERVE ERM/PHASE with EXEMPLAR/CORE)
HARDWARE ---- structural (pAsic targetted)
TESTING/LIST ---- listfil output of tests (V-SYSTEM/MODELTECH ?)
TESTING/TEST ---- testbenchs
SIM_LIB/PAsic20.VHD ---- gate models for structural simulation
Tests for VHDL / readme
Utilities for VHDL
VHDL Beautifier / EMACS Mode / Frontend / nicifier / pretty_printer_ADA / profiler (readme) / the_final_pretty_printer / UC VHDL - VHDL Grammar (yacc) (readme) / VHDL Parser (Prolog) / vhdl_1_2_1.vhdl / VHDL2C (Linux Binary) / VHDL93 BNF / VMKR & VSplit
